VitalyM4
Junior Member level 3
clock gating dft script cadence
Might be useful for someone.
RTL:
Best regards.
Might be useful for someone.
Code:
set_message_verbosity VLOGPT-035 off
read_verilog ./src/${RTL_FILE}
issue_message -type info "--> Start synthesis"
do_build_generic -module ${TOP_LEVEL}
set_current_module ${TOP_LEVEL}
set_top_timing_module ${TOP_LEVEL}
#PKS insert scan_chains
#Select scan_type
set_scan_style mux_scan
set_global dft_scan_avoid_control_buffering true
set_global dft_scan_path_connect tieback
set_scan_mode SCAN_EN 1
report_dft_assertions -all_modules
check_dft_rules
report_dft_registers
check_netlist
set_clock SCLK -period 80 -waveform {0 50}
do_optimize
set_global dft_scan_path_connect chain
set_number_of_scan_chains 1
set_scan_data -clock SCLK -rise SCAN_IN SCAN_OUT -enable SCAN_EN
do_xform_connect_scan
Code:
module frame_counter_no_scan (
SCAN_EN , /*Scan Enable*/
SCAN_IN , /*Scan Input*/
RSTB , /*Asynchronous reset*/
SCLK , /*Counter Clock*/
FRAME_CNT_INC_EN, /*Increment enable*/
FRAME_COUNT, /*Frame count*/
SCAN_OUT
);
/*Port direction and types*/
input SCAN_IN ;
input SCAN_EN ;
input FRAME_CNT_INC_EN;
output [7:0] FRAME_COUNT ;
output SCAN_OUT;
reg [7:0] FRAME_COUNT;
input SCLK ;
input RSTB ;
/*Internal signal declaration*/
wire rb ;
/*Functional description*/
/*disabled reset in SCAN mode*/
assign rb= RSTB;
/*Upward counter */
always@(negedge rb or posedge SCLK)
if(!rb)
FRAME_COUNT<={8{1'b0}};
else if(FRAME_CNT_INC_EN)
FRAME_COUNT<=FRAME_COUNT+1'b1; /*Normal mode*/
endmodule
Best regards.