Apr 27, 2021 #1 M msauer75 Newbie Joined Apr 21, 2021 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 51 Hi, in our design (Artix-7 200) I use an Aurora 8B10B core with the following parameters: I expect a tx_out_clk rate of 100MHz but it seems that isn't it. What is the correct clock rate? Thank you for your help. BR martin
Hi, in our design (Artix-7 200) I use an Aurora 8B10B core with the following parameters: I expect a tx_out_clk rate of 100MHz but it seems that isn't it. What is the correct clock rate? Thank you for your help. BR martin
Apr 27, 2021 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 The 100 MHz setting you have are for initialization and the dynamic reconfiguration ports. The data path is based on the GT Refclk which is 125 MHz in this case. 2,500,000,000 bps/120,000,000=20-bits ==> with 8b10b => 2-bytes (the lane width) Upvote 0 Downvote
The 100 MHz setting you have are for initialization and the dynamic reconfiguration ports. The data path is based on the GT Refclk which is 125 MHz in this case. 2,500,000,000 bps/120,000,000=20-bits ==> with 8b10b => 2-bytes (the lane width)