ATSC 8VSB Scrambler/Descrambler Design Question

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jgroleau

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Hi. I am in the process of writing a software scrambler/descrambler that is ATSC compliant. The A/53 standard has a brief description of how to do scrambling(randomizer). I have code written that will scramble and descramble a data stream. I have made some assumptions in the design that I would like to confirm are ATSC compliant. Any help would be appreciated verifying my assumptions.

1. Initialization value 0xF180 is shifted into the scrambler MSB First and it is shifted into the scrambler one bit at a time at the scrambler's LSB (i.e. Load to 1). This means the initial value of the scrambler is not 0xF180 but is the value obtained by shifting it into the scrambler.

2. Scrambler is shifted first and then taps are XOR'd with register outputs.

3. The initial Byte output of the scrambler is XOR'd with the first byte of the data segment.

4. Data segment bytes are not shifted into the scrambler. In other words the scrambler output is independent of the data stream.

5.Scrambler is shifted once per data segment byte.

Thanks.
 

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