[ATPG] Why the atpg patterns fail during simulation

[mysteriousandy]

Why the atpg pattern will fail in the simulation while TMAX generate the good patterns?
I'm confused about this. Could somebody elaborate more detail about it to me?

Thanks in advance

 

[jbeniston]

Timing violation?
Tmax models differ from Verilog models?

 

[mysteriousandy]

Timing violation?
Tmax models differ from Verilog models?

Yes, I also think these issues can produce the sim failure.
Did you encounter any other cases?
Somebody else can also comment about it.

Thanks

 

[maulin sheth]

Hello All,

Sometimes if u run simulation without timing,thn there is also chances for failing the patterns.
Because at the time of ATPG,we are giving some constraints and that may be not proper for simulation purpose but we are giving those Constraints to solve the ATPG DRC.
For that we have again cross check the constraints which we have given during ATPG.

Pl correct me if any misunderstanding?

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So basically, first we have to simulate the patterns without timing,So we can make sure that the functionality and patterns are working properly.
thn after we have to simulate design with the timing,so thereafter we can also conclude tht the issue is with timing or with the ATPG pattterns.

 

[mysteriousandy]

Do you mean that the constaints used to fix the DRC problem would lead the sim failure? Can you give me an example to clarify it ?
Then how do you fix this simulation issue?

Thanks very much

Hello All,

Sometimes if u run simulation without timing,thn there is also chances for failing the patterns.
Because at the time of ATPG,we are giving some constraints and that may be not proper for simulation purpose but we are giving those Constraints to solve the ATPG DRC.
For that we have again cross check the constraints which we have given during ATPG.

Pl correct me if any misunderstanding?

- - - Updated - - -

 

[maulin sheth]

Do you mean that the constaints used to fix the DRC problem would lead the sim failure? Can you give me an example to clarify it ?
Then how do you fix this simulation issue?

Thanks very much

To fix the simulation issue, we need to debug it using simulation waveform, what is exact source of the mismatch?
After getting the exact solution for mismatch,u can know the exact reason and also which constraints effect this mismatch.