Avrdan
Newbie level 1
atm design using vhdl
Hello,
I need to create a basic ATM machine for a school project
I need to make it work on an FPGA device. I currently own a digilent Basys board with the Spartan 3E chip.
I tried using a FSM approach.
I thought to make it work kind of this way:
Each switch, if active will automatically, by convention, activate one of the bank accounts in the "global" database. A green LED will then light up at the first clock cycle. If all switches are '0' or if another combination of the given one is entered a red one should light up and the circuit should not work further unless a "good" combination is entered.
I have created a memory in order to store the pin(authentification) codes :
- the pin numbers are stored, as 4 binary digits concataned into one 16 bit vector.
for example the first data line should represent:1234;
I wish to verify the corectness by using the following idea:
I created a 16 bit std_logic_vector and I use the same inputs, namely "I", which I then modify so that the user can enter a digit(four binary numbers, e.g.:"0001") at one clock cycle(I should concatenate the result to form the bigger, final vector). At 4 clock cycles the new vector should contain those 16 bits of information given as input by the user and I should then be able to verify the newly created vector with the one in the memory at a specific address.
However I do not exactly know how to read that from the memory. I tried declaring and instantiating a component, but something is definately wrong(as I get numerous warnings at synthesization regarding Aux and P_temp not being connected).
Here is the code of the main file:
Can anybody help me with this code, or perhaps suggest an alternative to the way I read and/or verify the pin codes which are introduced by the user.
First, I thought of programming a keyboard, however, while reading how to do that it seemes that it is a little to complicated for me at this point (and time consuming, otherwise I would have surely gotten the hang of it).
Best Regards,
Dan
P.S: I am using Xilinx ISE.
Hello,
I need to create a basic ATM machine for a school project
I need to make it work on an FPGA device. I currently own a digilent Basys board with the Spartan 3E chip.
I tried using a FSM approach.
I thought to make it work kind of this way:
Each switch, if active will automatically, by convention, activate one of the bank accounts in the "global" database. A green LED will then light up at the first clock cycle. If all switches are '0' or if another combination of the given one is entered a red one should light up and the circuit should not work further unless a "good" combination is entered.
I have created a memory in order to store the pin(authentification) codes :
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
----------------------------------------------------------------
Entity ROM2 is
Generic ( bits: INTEGER := 16; -- # nr of bits per word
words: INTEGER := 8); -- # nr of words in the memory
Port ( addr: in INTEGER range 0 to words-1;
data: out STD_LOGIC_VECTOR ( bits - 1 downto 0));
End ROM2;
----------------------------------------------------------------
----------------------------------------------------------------
Architecture ROM2 of ROM2 is
type vector_array is array (1 to words) of
STD_LOGIC_VECTOR (bits-1 downto 0);
Constant memory: vector_array := ( "0001001000110100",
"0001011000100100",
"0100000101010111",
"1000000100100100",
"0011001101010110",
"0010000101010011",
"0111000100100011",
"1001001001010110");
-- "00010011010010",
-- "10011100001111",
-- "01010000001100",
-- "10011010010100",
-- "00010101011101",
-- "01110110100111",
-- "00010010111100",
-- "01010011101001" );
begin
data <= memory(addr);
End ROM2;- the pin numbers are stored, as 4 binary digits concataned into one 16 bit vector.
for example the first data line should represent:1234;
I wish to verify the corectness by using the following idea:
I created a 16 bit std_logic_vector and I use the same inputs, namely "I", which I then modify so that the user can enter a digit(four binary numbers, e.g.:"0001") at one clock cycle(I should concatenate the result to form the bigger, final vector). At 4 clock cycles the new vector should contain those 16 bits of information given as input by the user and I should then be able to verify the newly created vector with the one in the memory at a specific address.
However I do not exactly know how to read that from the memory. I tried declaring and instantiating a component, but something is definately wrong(as I get numerous warnings at synthesization regarding Aux and P_temp not being connected).
Here is the code of the main file:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.The_Package.all;
use STD_LOGIC_UNSIGNED.all;
ENTITY simple_fsm IS
PORT ( clk, rst: IN BIT;
led_ok, led_pin_not_ok: out BIT;
I: IN std_logic_vector (7 downto 0));
END simple_fsm;
------------------------------------------------
ARCHITECTURE simple_fsm OF simple_fsm IS
COMPONENT ROM2 is
Generic ( bits: INTEGER := 16; -- # nr of bits per word
words: INTEGER := 8); -- # nr of words in the memory
Port ( addr: in INTEGER range 0 to words-1;
data: out STD_LOGIC_VECTOR ( bits - 1 downto 0));
End COMPONENT;
TYPE state IS (standby,AC,PIN,OP,Balance,Withdrawal,Print,P_Receipt);
SIGNAL pr_state, nx_state: state;
SIGNAL O: std_logic_vector(3 downto 0);
SIGNAL P,P_temp: std_logic_vector(15 downto 0);
SIGNAL Aux: INTEGER;
BEGIN
----- Lower section: -----------------------
PROCESS (rst, clk)
BEGIN
IF (rst = '1') THEN
pr_state <= standby;
ELSIF (clk'EVENT AND clk = '1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
--------------- Upper section: -----------------
PROCESS (pr_state,I,P_temp)
variable count,j,O_var2: INTEGER;
variable O_var: std_logic_vector (3 downto 0);
BEGIN
CASE pr_state IS
WHEN standby =>
-- PROCESS (I)
-- BEGIN
count := 4;
j := 1;
led_ok <= '0';
case I is
when "10000000" => O <= "0001";
when "01000000" => O <= "0010";
when "00100000" => O <= "0011";
when "00010000" => O <= "0100";
when "00001000" => O <= "0101";
when "00000100" => O <= "0110";
when "00000010" => O <= "0111";
when "00000001" => O <= "1000";
when others => O <= "0000"; led_pin_not_ok <= '1'; nx_state <= standby;
end case;
--END PROCESS;
O_var := O;
O_var2 := CONV_INTEGER(O_VAR);
Aux <= O_var2;
nx_state <= AC;
WHEN AC =>
if(I /= "00000000") then
led_ok <= '1';
end if;
for k in 0 to 3 loop
P(k+j) <= I(k);
end loop;
j := j+4;
count := count -1;
if(count /= 0) then
nx_state <= AC;
else nx_state <= PIN;
end if;
WHEN PIN =>
--U1: entity WORK.ROM2 PORT MAP (addr => Aux,data => P_temp);
if (P_temp /= P) then
led_pin_not_ok <= '1';
nx_state <= AC;
else
led_pin_not_ok <= '0';
nx_state <= standby; -- OP
end if;
--addr := CONV_INTEGER(O_var);
-- if(data(addr(CONV_INTEGER(O))) <= P) then
-- nx_state <=PIN;
-- end if;
WHEN others => null;
END CASE;
END PROCESS;
U1: ROM2 port map(addr => Aux,data => P_temp);
END simple_fsm;Can anybody help me with this code, or perhaps suggest an alternative to the way I read and/or verify the pin codes which are introduced by the user.
First, I thought of programming a keyboard, however, while reading how to do that it seemes that it is a little to complicated for me at this point (and time consuming, otherwise I would have surely gotten the hang of it).
Best Regards,
Dan
P.S: I am using Xilinx ISE.