zonks
Newbie level 3
I've been working with the Atmel ATF1508AS CPLD which supports different power supplies for the internal power (VCCINT, always 5V) and I/O pin power (VCCIO, can be 5V or 3.3V). I've developed several designs that work as expected with it.
Now I'd like to use the nearly identical Atmel ATF1508ASV CPLD which requires VCCINT=3.3V. The data sheet only describes VCCIO operation at 3.3V, but lists several timing parameters taken when VCCIO=5V. So I am making the assumption VCCIO can be 5V, though this is not explicitly stated in the datasheet.
In this case (VCCINT=3.3V, VCCIO=5.0V) the same designs randomly fail at power-up. When they do work, they continue to work (even after several hours of operation). So there is some kind of fault happening during power-up. The CPLD is somewhat warm but nothing excessive during correct operation.
Could it be a power sequencing issue? I use a 7805 regulator to provide 5V (VCCIO) and a 3.3V LDO regulator chained off that for 3.3V (VCCINT), so I suppose it's possible that VCCIO reaches 5V before VCCINT reaches 3.3V.
Any other ideas? Now I realize it's possible the chip does not support VCCIO=5V and the timing parameters in the datasheet with VCCIO=5V are a cut-and-paste error on Atmel's behalf, as the ATF1508ASV(L) data sheet is derived from the ATF1508AS(L) data sheet.
Conversely are there any special considerations when working with any part that has a lower internal voltage than its I/O voltage?
Now I'd like to use the nearly identical Atmel ATF1508ASV CPLD which requires VCCINT=3.3V. The data sheet only describes VCCIO operation at 3.3V, but lists several timing parameters taken when VCCIO=5V. So I am making the assumption VCCIO can be 5V, though this is not explicitly stated in the datasheet.
In this case (VCCINT=3.3V, VCCIO=5.0V) the same designs randomly fail at power-up. When they do work, they continue to work (even after several hours of operation). So there is some kind of fault happening during power-up. The CPLD is somewhat warm but nothing excessive during correct operation.
Could it be a power sequencing issue? I use a 7805 regulator to provide 5V (VCCIO) and a 3.3V LDO regulator chained off that for 3.3V (VCCINT), so I suppose it's possible that VCCIO reaches 5V before VCCINT reaches 3.3V.
Any other ideas? Now I realize it's possible the chip does not support VCCIO=5V and the timing parameters in the datasheet with VCCIO=5V are a cut-and-paste error on Atmel's behalf, as the ATF1508ASV(L) data sheet is derived from the ATF1508AS(L) data sheet.
Conversely are there any special considerations when working with any part that has a lower internal voltage than its I/O voltage?
