To simulate the whole chip, which level of the IO load capacitance would be reasonable.
Suppose the package type is CPGA. And how about the pcb capacitance, as I calculated since the thickness of the copper on PCB is very thin, the capacitance is only 0.04pF per centimeter.
Typically a value of load capacitance is specified in a device's data sheet for its listed dynamic characteristics. You might look at some typical data sheets for that value and use that as a simulation test capacitance.