Asynchronous VHDL state machines

Design of Asynchronous ciruits using VHDL

Hi ,

I am trying to implement an asynchronous microcontroller design in VHDL. I am totally new to asynchronous designs. I have read some basic concepts about single rail, dual rail, bundle data, mullerC element etc.
I am trying to use a 4 phase bundle data protocol for handshaking. I am using ISim for Simulation. I have a Program Counter module, a ROM module, and a Controller. My simulation completes in 0 time which is quite normal. So inorder to see the waveforms, i introduce delays inbetween handshaking signals in simulation. However, during synthesis, the delays will be ignored my the ISE synthesizer if I am right. And the entire execution of the design will complete in 0 time. So what are the hazards / glitches that I can expect. How should I overcome it ?

Also , are there any examples of VHDL State machines for a fully asynchronous designs ? Is it a good practice to use statemachines in a fully asynchronous design ? The examples that I have seen so far, illustrates only simple circuits with a few handshaking signals . Did i not look properly ? or Is it the most convinient and most preferred way to implement an asynchronous design ?

Please provide some input/ pointers in this direction. Would be much helpful.

Thank you ,


Venkat.

For any FIFO and State machine designs, Cummings papers Cliff Cummings' Award-Winning Verilog & SystemVerilog Papers - many are included in Sunburst Design's Verilog Training & SystemVerilog Training Courses. are the best to refer.

Hope this helps