Asynchronous state machine - Verilog synthesis question.

[ShiftRegister]

I am trying to build a block that ouputs a certain value initially (10) , and increments or decrements this value when input signals UP or DOWN are asserted (these are active low signals in my design). It just doesnt seem to work the way I want, although the code synthesizes on Quartus II.

Here is the code

module Threshold_Set(
  
   
   input UP,
   input DOWN,
   input clock,
   input tset, //hardware generated or external active low signal to set theshold value
   output restart,
   output [3:0] threshold 

);

assign restart = UP & DOWN;

reg [3:0] t_reg;

reg [2:0] counter;


assign threshold = t_reg;

always@(negedge UP or negedge DOWN or negedge tset)
begin

 if(tset==1'b0)
 begin 
 t_reg <= 4'b1010;
 end
 else
 begin

 if(UP == 1'b0)   //Why is UP signal taking it to unknown state?
 begin
  t_reg <= t_reg + 1;
 end
 
 else
 begin
  t_reg <= t_reg - 1;
 end
  
 end
end
endmodule

it seems to work for DOWN, but not for UP! or to consecutive DOWNs.

Can someone explain this mystery? [/code]

 

[FvM]

The code is not synthesizable. You can't build an asynchronous state machine with usual FPGA.
The state variable registers have to be triggered by one and only one clock edge. You can use synchronous
edge detection of UP and DOWN signals, with a sufficient fast clock.

 

[supercat]

Perhaps a quadrature-to-graycode converter would be useful. Start by converting your up/down counts into quadrature signals (one approach would be to have the 'up' and 'down' signals clock separate 2-bit graycode up-counters, and then convert the 4 bits from the two counters into a 2-bit quadrature value, being mindful of timing hazards). Call the quadrature signals q0 and q1. Signal q1 will be the lsb of the graycode count value.

Using transparent latches for all bits of the gray counter (other than the LSB, which can be skipped since it simply mirrors q1), latch into the bit to the left of the rightmost "1", or the leftmost bit if the rightmost bits are all "0", the xor of all the other bits, excluding q1 but including q0 (when computing this value for most bits, bear in mind that the bits to the right of the current bit will generally have exactly one "1" in them, so one can generally use the combinatorial value of a stage to the left in computing the desired xor).

The most significant bit of the binary output will equal the most significant bit of the graycode output. Each other bit of the binary output is the XOR of the corresponding bit of graycode output and the next-higher bit of the binary output.

The quadrature-to-graycode conversion may perform badly if q0 and q1 change too close together, but that should never occur if they are generated by an up/down count output as described earlier.