library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
entity fcnt is
port (
C : in std_logic;
S : in std_logic;
Q : out unsigned(7 downto 0));
end entity;
architecture RTL of fcnt is
constant MAX_CLK : integer := 250000000;
constant MAX_CNT : integer := 500;
signal count : unsigned(Q'range) := (others => '0');
signal toggle : std_logic := '0';
begin
clk_proc : process (C)
variable cnt_v : natural range 0 to MAX_CLK := 0;
begin
if rising_edge(C) then
if cnt_v = MAX_CLK then
Q <= count;
toggle <= not toggle;
cnt_v := 0;
else
cnt_v := cnt_v + 1;
end if;
end if;
end process;
cnt_proc : process (S, toggle)
variable cnt_v : natural range 0 to MAX_CNT := 0;
variable last_v : std_logic := '0';
begin
if toggle /= last_v then
last_v := toggle;
cnt_v := 0;
elsif rising_edge(S) then
if cnt_v < MAX_CNT then
cnt_v := cnt_v + 1;
end if;
count <= to_unsigned(cnt_v, count'length);
end if;
end process;
end RTL;