Asynchronous FIFO verification

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Mina Magdy

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Hi all
i have designed an asynchronous FIFO and i would like to verify it but i am little confused what technique is better using assertion based verification or using normal simulation based verification(normal test-bench) .
i would be glade if you could help me
 

If it is only a FIFO, then using a normal testbench is sufficient. Use an assertion based/methodology based testbench only if you intend to pick up any of the skills of writing complex testbenches.
 

If you understand assertion or SVA, it could be very efficient and tiny, especially for simple check like FIFO overflow/underflow. I disagree that assertion should be applied on complex testbenches only.
 
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