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Maybe we have a misunderstanding here. Do you mean asynchronous state machines? Combinatorial logic with feedback?Would you recommand it?
I understand it's done to save energy - right ?
I don't know about in a CPLD, but I can say that in an FPGA, with a reference design provided by a proponent of such things who was trying to patent some ideas in that area, the gated clock approach lost out badly to the synchronous approach. Used more power, ran more slowly...totally contrary to his claim. This was targetting Cyclone III/IV type devices. I suspect that the culprit on the power side is that the global clock resources in the FPGA have much lower capacitance and therefore consume much less power when switching that it came out ahead of the 'only clock when you need to' approach.Would you recommand it?
I understand it's done to save energy - right ?