I forgot to mention, that the ability to save power is primarly a matter of the involved CPLD family. In contrast to FPGA, most classical CPLD aren't "zero power", means up to several MHz clock statical power consumption (quiescent current) is higher than dynamical (clock related) power demand. With these types, power saving by asynchronous design techniques would be pointless.
On the other hand, classical CPLD macrocell logic arrays have less tendency to create glitches and also implement a very simple timing scheme, so it's much easier to create reliable asynchronous circuits than with FPGA, at least in manual design. Missing support of asynchronous circuit timing analysis also affects HDL CPLD design.