Asynchronous Combination Lock

[dandygal]

Hi,
I need to design a systems using Xilinx Schematics with the following specifications:

This combination lock has a minimum sequence of four two-bit input symbols as the combination
and appears to the user as if it is an asynchronous circuit. Actually, it is a synchronous circuit
with a fast clock and synchronization of the user inputs. For a given input combination, the circuit
goes to a state and cycles there until the input changes to a new symbol; thus, the combination
cannot contain consecutive appearances of the same symbol. The lock is locked by using an
asynchronous RESET.

Here is a sample implementation of the problem:

photo

I need to understand the logic behind it. Can you explain me whatever you can make out from this information?

Thanks,

 

[lucbra]

We are not here to do your homework, however:
1. analyze the example
2. try to understand your task
3. draw something on paper
4. post it here

then maybe somebody will give some comments

 

[dandygal]

The project is already done. It's overdue. I'm simply trying to understand how it works by the solution given to us.

 

[TrickyDicky]

What specific questions do you have? its quite clear given the logic diagram - what dont you understand?

 

[dandygal]

Specific questions:
1) It says that "a minimum sequence of four two-bit input symbols". Does it mean that it will hold 4 consequent 2-bit input in its memory and if the sequence is correct give 1 output?
2) How can i see the password on the design? (8 digit, I assume)
3) What does it mean the combination cannot contain consecutive appearances of the same symbol?
4) How come it looks like asynchronous but it's actually not?
Overall how does the design relate to the problem? (all the AND OR gates and D-ffs)
I'm an absolute beginner and I can't make sense of all these. That's why it was hard for me to even come up with proper questions.
I'd really appreciate any help.

 

[mrflibble]

Specific questions:
1) It says that "a minimum sequence of four two-bit input symbols". Does it mean that it will hold 4 consequent 2-bit input in its memory and if the sequence is correct give 1 output?

No, it does not mean that. Pr0-tip: count the number of flip-flops in the schematic you attached.

4) How come it looks like asynchronous but it's actually not?

Actually at first glance it looked like it might have a chance of being synchronous (but with combinational logic that goes straight to the output). But then I traced back from those 4 AND inputs and it actually is async. Just wiggle S0 real fast and see how "synchronous" it is.