dft123
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I have design with async reset. This is async in assertion and sync in de-assertion. Also, the output of the synchronizers is ORed with a top level dftrstdisable port which behaves the same way as scan enable. This is done to avoid any reset issues during shift. In capture, the reset can toggle to acheive coverage on the synch paths.
I am using Mentor tools for insertion/atpg.
Question is:
How do i handle/define the async reset to the tool? Do I declare the async reset as clocks during scan insertion?
I am using Mentor tools for insertion/atpg.
Question is:
How do i handle/define the async reset to the tool? Do I declare the async reset as clocks during scan insertion?