What's the difference in the following codes implementation (two pieces of code)?
Let's assume that the reset (rstn) happens only once... So, is there a difference in the code implementation/behavior?
Code:
----------------------------------------------------------------------
signal Q : std_logic := '0';
process (clk) is
begin
if rising_edge(clk) then
Q <= IN;
end if;
end process;
Code:
----------------------------------------------------------------------
signal Q : std_logic;
process (clk,rstn) is
begin
if falling_edge(rstn) then
Q <= '0';
elsif rising_edge(clk) then
Q <= IN;
end if;
end if;
end process;
I don't understand the question. The first snippet has no reset action at all. Also the second code does not implement an asynchronous reset. Instead it has two edge sensitive conditions which aren't synthesizable in usual programmable logic hardware.
Contradicting maxbjurling, it should be noticed that most logic synthesis tool do synthesize initialization statements as power-on reset. But it's no exactly the same as an external reset input because you can't control its timing, it's e.g. not possible to release it synchronous to a clock.
FvM, this may be true for FPGA tools but ASIC synthesis tools ignore initial assignments. And this thread is in the "ASIC Design Methodologies and Tools" section.