assign read_data = fifo_data[read_ptr[ADDR_WIDTH-1:0]];
always @ (posedge read_clock)
begin
read_data <= fifo_data[read_ptr];
end
Say it doesn't work in your present design. Didn't claim it should, just stated that industry standard async FIFO will read the dual port RAM synchronously.I have confirmed that your suggestion above does not work when read_clk domain has a higher clock frequency compared to write_clk domain
always @(posedge read_clk)
begin
if(reset_rsync) read_data <= 0;
else if(!empty) read_data <= fifo_data[read_ptr[ADDR_WIDTH-1:0]]; // passed verilator Warning-WIDTH
end
There are probably not enough entries considering the delay involved with cross domain sync. If the problem persists after increasing the number of entries, I'd suspect faulty full/empty logic.Why is full being asserted when write_clk is slower than read_clk , and there are enough fifo storage entries ?
No, see https://github.com/promach/afifo/blob/b8092eb84914e96a1fa4c024e3c0b2962770b26c/async_fifo.v#L187Does your FIFO spec allow write in full respectively read in empty state?
There are probably not enough entries considering the delay involved with cross domain sync.
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