assura qrc setting : use field solver or not

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guow06

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i am using tsmc90nm technology. my design is sensitive to parasitic capcitance, so when i do layout extraction, should i use the assura field solver or not? (rcxfs.dat is provided in the design kit.)
 

It depends on several factors, like:

- what extraction accuracy are you looking at?
- are you concerned about the absolute value of parasitic capacitances, or about the capacitance mismatch in precision analog?
- would field solver be capable of simulating (i.e. extracting) a large design (large nets)
- etc.
 

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