Sep 2, 2013 #1 E eeStud Member level 1 Joined Feb 17, 2011 Messages 37 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,527 Hi, When i am running Assura LVS i am getting mismatch between layout & schematics regarding the top cell pins (the pins are at the beggining of the top cell SUBSET definition in the cdl file). How can i prevent this mismatch? Thanks.
Hi, When i am running Assura LVS i am getting mismatch between layout & schematics regarding the top cell pins (the pins are at the beggining of the top cell SUBSET definition in the cdl file). How can i prevent this mismatch? Thanks.