Assura LVS error: Bad Initial Net Bindings

[mmohsen]

while i was doing LVS using (Assura) ,i finshed fixing all the errors and this message appears to me :

Unknown LVS error found
see test.cls file for details.

what does it mean ???

and i opened the .cls file and find that :

====================================================================[bias_nmos]
====== Problem Layout Nets (no exact match in schematic) ======================
===============================================================================
L
L ?gnd
L 16 of NMOS4 {D S}
L 1 of NMOS4 G
L 16 of NMOS4 B
L 1 of INV6 gnd
L 3 of NMOS4arMos2#1 {OUT OUT2}
L 3 of NMOS4arMos2#1 TERM4
L 2 of NMOS4arMos2#1 {IN1 IN2}

====================================================================[bias_nmos]
====== Summary of Errors ======================================================
===============================================================================

Schematic Layout Error Type
--------- ------ ----------
1 1 Bad Initial Net Bindings



Regards,..

 

[franck]

assura bad initial net bindings

Hi,

Did you fix your problem?

 

[rajavel]

assura bad net

When you encounter a error as Bad initial net binding, there might be a wrong connection wrt input port, input may be shorted to other nets also.
First ensure your schematic is correct and check for the input nets in your layout.

 

[franck]

assura pin binding

"When you encounter a error as Bad initial net binding, there might be a wrong connection wrt input port, input may be shorted to other nets also.
First ensure your schematic is correct and check for the input nets in your layout."

The problem here is that Assura deliver a "unknow lvs error"!!!!
If there is really a short, it's a short, that's all. In this case in fact ...
There is different reason to have this "unknow lvs error"> One of them is huge differential circuit. Assura is not able (after all this year of developpement on diva???) to find the pin to swap and just give this message. But by reading the lvs report you can "guess" what the problem is.
Another reason is the definition of the devices in the deck. Some new kit must be fix on some device as RFMOS. It happened to me that a bad definition of a device in the kit deliver this message in Assura. There is problably a lot of other reason. And that for that I just asked initially if the problem has been fixed.
It can become a thread: UNKNOW LVS PROBLEM REASONs: LET'S DEBUGGING ASSURA!!