Assigning to a parameterized 2d Verilog array

shaiko · Sep 6, 2020

Hello,

I have a Verilog array defined as :
logic [0:num_elements-1] [element_width] some_array ;

I want to assign every array element with a vector that is all ones: "11...1".
I tried this but I get an error:

Code:

some_array <= { num_elements { element_width { 1'b1 } } } ;

What's the correct syntax ?

dpaul · Sep 7, 2020

I am not a Verilog guy.....

But can't you assign each elements of the array inside a double-loop?

shaiko · Sep 7, 2020

I can, but I'm looking for a single liner - like VHDL's :

Code:

some_array <= ( others => ( others => '1' ) ) ;

ads-ee · Sep 8, 2020

Just assign it directly as you defined it as a packed array format

Code Verilog - [expand]
1
some_array <= {num_elements*element_width{1'b1}};

--- Updated Sep 8, 2020 ---

If you had defined it using an unpacked array format then you would use a for loop to set each element.

Assigning to a parameterized 2d Verilog array

shaiko

Advanced Member level 5

dpaul

Advanced Member level 5

shaiko

Advanced Member level 5

ads-ee

Super Moderator

shaiko

Similar threads

Code Verilog - [expand]
1	some_array <= {num_elements*element_width{1'b1}};

Assigning to a parameterized 2d Verilog array

shaiko

Advanced Member level 5

dpaul

Advanced Member level 5

shaiko

Advanced Member level 5

ads-ee

Super Moderator

Similar threads

Privacy & Transparency

Privacy & Transparency