[SOLVED] Assigning indexed INPUTs to indexed OUTPUTs in VHDL

[Farid Shamani]

Dear Friends,
I have number of inputs and outputs as:

inp0
inp1
inp2 ... to inp255

and outputs:
outp0
outp1
outp2 ... to outp255

I want to assign them together in a way other than assigning one by one, which will take 256 times of assignments
(e.g. outp0 <= inp0; outp1 <= inp1; and so on to outp255<= inp255)

Is there any possibility to do this, for example, in a FOR loop?

Thank you

 

[K-J]

I have number of inputs and outputs as:

inp0
inp1
inp2 ... to inp255

and outputs:
outp0
outp1
outp2 ... to outp255

I want to assign them together in a way other than assigning one by one, which will take 256 times of assignments
(e.g. outp0 <= inp0; outp1 <= inp1; and so on to outp255<= inp255)

Is there any possibility to do this, for example, in a FOR loop?

You can't use a loop because you have nothing to index on. What you need to do is make 'inp' and 'outp' be vectors of whatever type you have. Then the assignments would be

out <= inp; -- Regardless of the type or the size of 'inp' and 'out'...other than that they are the same size and type.

Kevin Jennings

 

[Farid Shamani]

Thank you Kevin

But what if i want to connect inputs number 15 to 0, to output number 15 to 31? I have to manipulate the vectors?!?
and one more Q, do i have to declare all 256 inputs and 256 outputs in ENTITY part or i can assume a vector for them as well? I think i should assume it.

 

[K-J]

Thank you Kevin

But what if i want to connect inputs number 15 to 0, to output number 15 to 31? I have to manipulate the vectors?!?

In that case, you may want to write a function which would likely then have a for loop in it.

and one more Q, do i have to declare all 256 inputs and 256 outputs in ENTITY part or i can assume a vector for them as well? I think i should assume it.

Everything must be declared, there are no assumptions. If these 256 are I/O of the entity, then yes they need to be defined in the entity.

Kevin Jennings

 

[FvM]

You are talking about vectors without defining the ports as such. Doing so would be a reasonable first step, because it's the prerequisite for any kind of indexing or computed signal mapping.