1)the expression"(a+b<<1)" and "a+(b<<1)" will be sythesized to the same circuits when a, b is more than 1 bit?
if i am not wrong, a+b<<1 means (a+b)<<1, so it is different than a+(b<<1).
DC will synthesis a different logic for the two expression.
2)Is it always better to let synthesis too decide when to use resource sharing based on design constraint?
Base on my experience, it is better you decide the initial architecture for the data flow based on your requirement. new version of DC can do some job for you, but you can not control it.
3)will the unused input be tied by synopsys design compiler automatically?
boundary optimization will remove unnecessary logic, but if you do not specify, the port will be kept, but will not connected.
4) Does the gated clock refer to a clock network that contains Boolean functions other than buffers and inverters in synopsys design compiler?
and Does teh gated clock network have to be explicitly defined in synopsys design compiler?
5)Must the derived clocks be specified explicitly for synthesis in synopsys design compiler?
yes. usually you should seperate clock generator logic from the synthesis since you need other tools or manually handel the clock path.