[ASK][Roles of guard-ring in triple well device]

Hi..

I want to know that roles of n+, p+ guard ring.

I only know that n+ ring must be connected VDD and p+ ring must be connected GND.

I wonder that how n+ or p+ guard ring blocks the noise component (e.g. digital switching noise).

thank you !

This is semiconductor technology, latchup prevention. The N polarized metal attracts electrons, these electrons leave empty whole in the P metal. In truth, there are only electrons that move from P to N, but we use the term whole in order to describe that.

You can see more here.

N+ in Pepi makes a depletion region which
can sweep out minority carriers that enter
its influence. Tied locally (sub! / vss!) it will
have a smaller depletion volume but return
substrate carriers to the substrate terminal.
Tied to vdd! it will present a larger "collection
target", hopefully a few charges more or less
won't bother the supply. But there are some
environments where much more substrate
carriers are generated.

The more "taps", the less deflection the well
or local substrate region will deflect from its
proper potential when presented with
displacement currents from parasitic
capacitances' node slewing. Voltage excursions
can enter the designed circuit by the "body
effect". A guardring is the most effective "tap"
geometry (fatter and closer is better).

Besides the points described above, it also provides a way to have an isolated Pwell in case you want to have a NMOS device not directly over substrate