peter_hawk
Newbie level 4
I want to design a differential to single-ended amplifier.
Input: 0~vdd full swing 500MHz sine wave (vdd=2.7v, 0.5um cmos tech)
The circuit is as following.
My question is the output is not at 50% duty cycle
Can anyone give me some advise.
Input: 0~vdd full swing 500MHz sine wave (vdd=2.7v, 0.5um cmos tech)
The circuit is as following.
My question is the output is not at 50% duty cycle
Can anyone give me some advise.