ASITIC, tek files and KCL violation

[Beardolphinaries]

Hi, I've got two questiona about ASITIC.

1. Do any one have 0.12um CMOS tek files for ASITIC?

2. After I draw a square inductor and use pix to test it. why there are 'KCL violation' warming for the last two segments? This might be a problem if I want to flip and flipphase the inductor.

Thanks a lot.

 

[nafraf]

Hi, do you try to write the TEK file using the process technology documentation? It's not hard.

 

[Beardolphinaries]

Hi, thanks for help.

I did a study of the TEK file. The problem is that I don't have a process technology documentation. Do you know where I can find this kind of documentation? Just standard one is OK. Thanks.

 

[nafraf]

Hi, the process technology is confidential. So, in order to get the process documentation your institution will have to sign an NDA with the foundry.

 

[Beardolphinaries]

Oh, I see, thanks a lot for help