vanshlata
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Hello everyone,
I am a B.tech ECE graduate and I did a 6 month PG DIPLOMA in ASIC DESIGN and VERIFICATION from NIELIT, Calicut.
I am currently looking for an entry level job in the same domain, but have had no luck.
Will appreciate if I can get any guidance and helpe with the people on this website.
TECHNICAL (IT) SKILLSET
LANGUAGES :
Verilog HDL with basic scripting techniques using SHELL and PERL scripting language
Basics of SYSTEM VERILOG for verification.
Programming through C/Assembly
Basics of VHDL
Ladder language for Programming of PLC’s like Allen Bradley, Siemens, Omron
Basics of MATLAB
EDA TOOLS :
SYNOPSIS TOOLS-DVE and VCS for Design and Verification, Design Compiler for synthesis, Xilinx ISE(12.1_2) for FPGA Prototyping
PYXIS LAYOUT for Backend design
CALIBRE for verification
MODELSIM(10.1SE) for RTL Coding, Design and Verification in Verilog
QUESTASIM for RTL Coding, Design and Verification in SystemVerilog
LEONARDO SPECTRUM(LS2012b_6) for Synthesis
SCADA for interfacing
I am a B.tech ECE graduate and I did a 6 month PG DIPLOMA in ASIC DESIGN and VERIFICATION from NIELIT, Calicut.
I am currently looking for an entry level job in the same domain, but have had no luck.
Will appreciate if I can get any guidance and helpe with the people on this website.
TECHNICAL (IT) SKILLSET
LANGUAGES :
Verilog HDL with basic scripting techniques using SHELL and PERL scripting language
Basics of SYSTEM VERILOG for verification.
Programming through C/Assembly
Basics of VHDL
Ladder language for Programming of PLC’s like Allen Bradley, Siemens, Omron
Basics of MATLAB
EDA TOOLS :
SYNOPSIS TOOLS-DVE and VCS for Design and Verification, Design Compiler for synthesis, Xilinx ISE(12.1_2) for FPGA Prototyping
PYXIS LAYOUT for Backend design
CALIBRE for verification
MODELSIM(10.1SE) for RTL Coding, Design and Verification in Verilog
QUESTASIM for RTL Coding, Design and Verification in SystemVerilog
LEONARDO SPECTRUM(LS2012b_6) for Synthesis
SCADA for interfacing
