asic flow - fix violations

[ee1]

is there a recommended method for reparing violations (timing and drc)?

i mean, should i check before starting any step (placement, cts, routing) that the design is "clean", or i can run the flow, and
after route start fixing them?

i am guessing i should have cleandesign before starting each step...but want to know what you guys think...

thanks!

 

[ljxpjpjljx]

you mean hold time or setup time violation?

 

[kbulusu]

Ideally speaking you should proceed to next stage only after you fix the violations after each respective stages...but if there are only few handful violations and depending on how large or small the viol, you can choose to proceed to next stage...but after CTS, it only tends to become worse...also it really depends on what kind of viol it is and we need to look and analyze the path before we can recommend what to do next...

now you need to ideally fix all the setup violations before CTS stage and fix both setup and hold after each stage of CTS...after routing and post SI..its very difficult to close timing..if you choose to fix very late, then what would you do if you see the viol is because of the bad placement..you cannot touch placement as clock network is already built..any changes you do after routing is very costly..

Last alternative which most people do is fix via eco ...you can do this if you want to...now there are couple of types of eco and each has it adv and dis-adv and where you are in the TO train...

hope this helps...good luck..

 

[ee1]

Thanks for the answers!
Can you elaborate on the eco types please?

 

[kbulusu]

metal only eco - using either spare gates/gate arrays
timing eco
logical eco

What each of them can be found in google and so dont want to duplicate here again..good luck..