melomon
Newbie level 1
Leading fast growing high-end digital video company in Sunnyvale, CA, is looking for the following talented ASIC engineers.
More than competitive salaries and solid benefits .This is the company that employees are proud of! Send your resume to "melomon AT yahoo DOT com"
ASIC Engineer, Digital/Video Design
BSEE (MSEE preferred) with 10 years industry experience.
Tools experience desired:
Verilog simulators (such as Cadence's NC_Verilog),
Synthesis tools (such as Synopsys' Design Compiler, Physical Compiler),
Test insertion/ATPG tools (such as Synopsys' DFT Compiler, TetraMax),
Logic equivalence tools (such as Cadence's (Verplex) Conformal-LEC),
Static timing tools (such as Synopsys' PrimeTime),
Verification tools (such as Verisity's SpecMan),
Familiarity with layout tool flow and engineering support thereof (floorplanning, clock tree generation, constraints translation, LVS, DRC)
Skills experience desired:
Hardware/verification languages (verilog, e),
software (C, Perl, Tcl, other scripting languages).
Other Skills:
Hands on Lab Skills;
Silicon bring up and checkout using 'Scope and Logic Analyzer.
ASIC FPGA Engineer, Digital Design
BSEE with 5 years industry experience
Tools experience desired: Verilog simulators (such as Cadence's NC_Verilog), Synthesis tools (such as Synopsys' Deisgn Compiler, Synplicity), Logic equivalence tools (such as Cadence's Verplex) Conformal-LEC, Static timing tools (such as Synopsys' PrimeTime), Schematic Capture tools (OrCad).
Familiarity with board layout tool flow and eningeering support thereof is required.
Hands on Lab Skills; Scope and Logic Analyzer requires.
Board bring-up and debug skills required.
ASIC Verification Manager, CE LOB
A strong background in ASIC verification is required for this position. Previous verification architecture and implementation experience and current hands-on capabilities are expected. A strong knowledge of ASIC design and manufacturing test methods is also required. Areas of verification experience desired include high-level verification environment architecture, verification model specification and implementation, and verification matrix and regressions site development. Technology background desired includes digital video processing, digital audio processing, real-time data transfer, TMDS and other analog block modeling. A working knowledge of state-of-the-art verification methods and tools is required. Knowledge of the digital design flow (tools and methods) is desired. The person needs to be a strong leader who is self-motivated, exhibits excellent skills in both written and oral communication, and works well with a team of other managers and individual contributors from verification, digital design, analog design, system engineering/architecture, and test engineering.
BSEE (MSEE preferred)
8+ years industry experience
Management tools experience desired: Microsoft Project, Excel, Word, PowerPoint
Verification tools experience desired: High-level verification languages, particularly Verisity Specman ‘e’, Veilog simulators (such as Cadence’s NC-Verilog), scripting and programming tools such as Perl, sch, and TCL. Test insertion/ATPG tools (such as Synopsys’ DFT Compiler, TetraMax)
ASIC Design Engineer
BSEE (MSEE preferred) with 5 years industry experience.
Tools experience desired: Verilog simulators (such as Cadence's NC_Verilog), Synthesis tools (such as Synopsys' Design Compiler, Physical Compiler), Test insertion/ATPG tools (such as Synopsys' DFT Compiler, TetraMax), Logic equivalence tools (such as Cadence's (Verplex) Conformal-LEC), Static timing tools (such as Synopsys' PrimeTime), Verification tools (such as Verisity's SpecMan), familiarity with layout tool flow and engineering support thereof (floorplanning, clock tree generation, constraints translation, LVS, DRC)
Skills experience desired: hardware/verification languages (verilog, e), software (C, Perl, Tcl, other scripting languages).
Other desired skills: Hands on Lab Skills; 'Scope and Logic Analyzer.
More than competitive salaries and solid benefits .This is the company that employees are proud of!
More than competitive salaries and solid benefits .This is the company that employees are proud of! Send your resume to "melomon AT yahoo DOT com"
ASIC Engineer, Digital/Video Design
BSEE (MSEE preferred) with 10 years industry experience.
Tools experience desired:
Verilog simulators (such as Cadence's NC_Verilog),
Synthesis tools (such as Synopsys' Design Compiler, Physical Compiler),
Test insertion/ATPG tools (such as Synopsys' DFT Compiler, TetraMax),
Logic equivalence tools (such as Cadence's (Verplex) Conformal-LEC),
Static timing tools (such as Synopsys' PrimeTime),
Verification tools (such as Verisity's SpecMan),
Familiarity with layout tool flow and engineering support thereof (floorplanning, clock tree generation, constraints translation, LVS, DRC)
Skills experience desired:
Hardware/verification languages (verilog, e),
software (C, Perl, Tcl, other scripting languages).
Other Skills:
Hands on Lab Skills;
Silicon bring up and checkout using 'Scope and Logic Analyzer.
ASIC FPGA Engineer, Digital Design
BSEE with 5 years industry experience
Tools experience desired: Verilog simulators (such as Cadence's NC_Verilog), Synthesis tools (such as Synopsys' Deisgn Compiler, Synplicity), Logic equivalence tools (such as Cadence's Verplex) Conformal-LEC, Static timing tools (such as Synopsys' PrimeTime), Schematic Capture tools (OrCad).
Familiarity with board layout tool flow and eningeering support thereof is required.
Hands on Lab Skills; Scope and Logic Analyzer requires.
Board bring-up and debug skills required.
ASIC Verification Manager, CE LOB
A strong background in ASIC verification is required for this position. Previous verification architecture and implementation experience and current hands-on capabilities are expected. A strong knowledge of ASIC design and manufacturing test methods is also required. Areas of verification experience desired include high-level verification environment architecture, verification model specification and implementation, and verification matrix and regressions site development. Technology background desired includes digital video processing, digital audio processing, real-time data transfer, TMDS and other analog block modeling. A working knowledge of state-of-the-art verification methods and tools is required. Knowledge of the digital design flow (tools and methods) is desired. The person needs to be a strong leader who is self-motivated, exhibits excellent skills in both written and oral communication, and works well with a team of other managers and individual contributors from verification, digital design, analog design, system engineering/architecture, and test engineering.
BSEE (MSEE preferred)
8+ years industry experience
Management tools experience desired: Microsoft Project, Excel, Word, PowerPoint
Verification tools experience desired: High-level verification languages, particularly Verisity Specman ‘e’, Veilog simulators (such as Cadence’s NC-Verilog), scripting and programming tools such as Perl, sch, and TCL. Test insertion/ATPG tools (such as Synopsys’ DFT Compiler, TetraMax)
ASIC Design Engineer
BSEE (MSEE preferred) with 5 years industry experience.
Tools experience desired: Verilog simulators (such as Cadence's NC_Verilog), Synthesis tools (such as Synopsys' Design Compiler, Physical Compiler), Test insertion/ATPG tools (such as Synopsys' DFT Compiler, TetraMax), Logic equivalence tools (such as Cadence's (Verplex) Conformal-LEC), Static timing tools (such as Synopsys' PrimeTime), Verification tools (such as Verisity's SpecMan), familiarity with layout tool flow and engineering support thereof (floorplanning, clock tree generation, constraints translation, LVS, DRC)
Skills experience desired: hardware/verification languages (verilog, e), software (C, Perl, Tcl, other scripting languages).
Other desired skills: Hands on Lab Skills; 'Scope and Logic Analyzer.
More than competitive salaries and solid benefits .This is the company that employees are proud of!