Hello, one question when we use Dual port BRAM as a interface to DDR3, A side port can be 8 bit port and B side port 128bits, and address respectively 11bits and 8bits, when FrameValid and LineValid is ON, data is available, so that time address increase to 1, and write enable is 1 when data valid . and B side has 128bits wide which connects to DDR3, how to write B side address, there only 8bits address, maximum is 256 addresses can be, write Aside based on camera's FrameValid and Line valid , but Bside can be based on what ?
and i found several tutorial where use FSM machines write and read from DDR3 by only one clock , it can be used 2 clock domains and two FSMs ?