You'll need to process the ADC frame clock (FCO) somehow in your design. One possible way is to use only FCO and generate the bit clock internally by a PLL.
I presumed it as obvious. In fact I'm suggesting to use FCO instead of DCO. If you review some SERDES application examples, you'll realize that this is common practice. The other option is to use both DCO and FCO. I'm not familiar with Xilinx SERDES IP and don't know if it's supported,I forgot to say that I have bit clock coming from ADC.
The bitslip function may be used, but FCO must be connected to your logic in any case. Did you try to simply connect FCO as DIVCLK?
You can use the bitslip, or implement the feature in fabric if you want. How are you connecting the ISERDES clocks and resets?
If you have bit slip due to different clocks/data trace lengths or internal delays, you may want to use the SPI interface to the ADC to put the device into test mode, and then send out a basic: 10101100 sequence which can be used to calibrate the unit. There are SPI controllers online, or you could use an existing computer to fpga control interface (if you have one) to just bit-bang the io lines. (unless the SPI interface can timeout, check the datasheet).
Before you connect multiple lines of the SPI interface, you could also consider to use FCO.
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