Artix7-ADC interface problem

[eren000]

Hello, i am trying to interface an adc(AD9287) to my artix 7 device. Adc gives serial lvds output. I am using iserdes (selectio) module but the problem is i do not know exact starting time of adc output so there is word framing error. İ could not catch the correct 8 bit, rather their shifted version by random amount of bits. Any idea to correct this? İs bitslip function proper for my problem? Thanks.

 

[eren000]

You'll need to process the ADC frame clock (FCO) somehow in your design. One possible way is to use only FCO and generate the bit clock internally by a PLL.

Thanks for quick response.
I forgot to say that I have bit clock coming from ADC. there is no problem with getting correct bits. Only problem is framing.
For example , assume we have incoming 2 byte data serially from ADC: 01101111 00010101
What I get is something like that: xxxx0110 11110001 0101... it goes on like that. How can I solve this framing error?

 

[FvM]

You'll need to process the ADC frame clock (FCO) somehow in your design. One possible way is to use only FCO and generate the bit clock internally by a PLL.

- - - Updated - - -

I forgot to say that I have bit clock coming from ADC.

I presumed it as obvious. In fact I'm suggesting to use FCO instead of DCO. If you review some SERDES application examples, you'll realize that this is common practice. The other option is to use both DCO and FCO. I'm not familiar with Xilinx SERDES IP and don't know if it's supported,

 

[eren000]

I feel like that the solution to my problem is bitslip function of Xilinx serdes Ip. I will consider your valuable advices and still I am waiting for others related to bitslip logic. Thanks.

 

[FvM]

The bitslip function may be used, but FCO must be connected to your logic in any case. Did you try to simply connect FCO as DIVCLK?

 

[eren000]

The bitslip function may be used, but FCO must be connected to your logic in any case. Did you try to simply connect FCO as DIVCLK?

Nope, I never use FCO, in fact I could not find a way to use FCO in order to adjust bitslip accordingly.

 

[vGoodtimes]

You can use the bitslip, or implement the feature in fabric if you want. How are you connecting the ISERDES clocks and resets?

If you have bit slip due to different clocks/data trace lengths or internal delays, you may want to use the SPI interface to the ADC to put the device into test mode, and then send out a basic: 10101100 sequence which can be used to calibrate the unit. There are SPI controllers online, or you could use an existing computer to fpga control interface (if you have one) to just bit-bang the io lines. (unless the SPI interface can timeout, check the datasheet).

 

[FvM]

Activating the test mode would be appropriate for a SERDES with phase align feature to shift the bit clock to the center of the sampling window. The simple task of alligning the word frame correctly should work well without it.

Of course, if the design misses to connect the frame clock, it may be a workaround.

 

[eren000]

You can use the bitslip, or implement the feature in fabric if you want. How are you connecting the ISERDES clocks and resets?

If you have bit slip due to different clocks/data trace lengths or internal delays, you may want to use the SPI interface to the ADC to put the device into test mode, and then send out a basic: 10101100 sequence which can be used to calibrate the unit. There are SPI controllers online, or you could use an existing computer to fpga control interface (if you have one) to just bit-bang the io lines. (unless the SPI interface can timeout, check the datasheet).

I connect DCO of ADC to ISERDES clocks. Reset signals will be generated inside the FPGA. I have no problem with trace lenghts, delays etc. The only problem is word framing and it seems I do not have a choice but SPI, right?

 

[FvM]

Before you connect multiple lines of the SPI interface, you could also consider to use FCO.

 

[eren000]

Before you connect multiple lines of the SPI interface, you could also consider to use FCO.

That is exactly what I want to do but I could not find a way to use FCO to correct frames.

 

[FvM]

As I said, I'm no working with Xilinx and don't know the SERDES details. At first look, it seems like connecting FCO to DIVCLK would to the trick.

 

[vGoodtimes]

There are some details with the enable/reset lines. For high speed interfaces, there can also be issues with PCB layouts or input delay calibration, especially if the input clock was connect to a pin that can't directly clock the IO. If you can't get the FCO to work for framing, I'm not sure how you can determine there are no issues with the reset scheme, pcb, select io features, etc... It also isn't clear if you are doing static analysis on the inputs, or if you have an active calibration system.

What happens when you use the FCO with the ISERDES? you should have data that is consistently shifted by the same amount every time. (or alternates between 2 adjacent bit periods).

Getting a control interface working is very useful for other reasons. A good system will be able to provide not just a "link up", but be able to provide information about the "link margin". I've given up on just hoping an interface works based on good design practice. Too many times there is an odd issue and re-building/re-testing takes too long. (undocumented feature, bad cable, bad prototype, etc...) The advantage to having the control interface is that you know the system works, know the margin, and can compare it to other units. Every time the ability to debug the interface has come up after the initial bringup as well.

 

[eren000]

Yes, basically I have data shifted by random amount at every power up. I have to use bitslip to correct the frame but this amount is changing every power up.

It seems the only solution is SPI interface which I do not want to use because of complexity. As you mention, it gives robustness to system. What I was looking for is a trick to correct data framing but I guess it will not be possible , right?

 

[FvM]

You didn't yet tell why you don't connect FCO to the SERDES as erverybody does.

 

[ads-ee]

If you use the bit clock (DCO) and bitslip it's pretty much mandatory that you include a training sequence in your strartup to find the framing.

I don't understand why you would think using SPI to enable testmode and the training pattern would be all that difficult. SPI is a very simple protocol and in this case you don't care about doing anything more than writing to 0xD twice once to enable test mode and once to disable it. This could easily be done using a simple FSM (i.e. no master SPI controller) and hard coding the 0xD register values sent to the ADC.

But as others have already suggested, why don't you use FCO? This is what Xilinx recommends per their own application note XAPP585.

 

[eren000]

SPI seems complicated to me , I dont know maybe its because I never use it. From now on I will consider to use SPI then.

I dont use FCO because I did not know how to use it. I am just taking incoming data with DCO and taking output of SERDES. I dont have any clue related to usage of FCO. I am relatively inexperienced in FPGA area, maybe that is the answer
Thanks for your time!