[SOLVED] Array instantiation in verilog

[gnoble29]

How can I instantiate an array in verilog?

For example, I Have an array a[0:10] in my top module.I want to pass this a[0:10] into another submodule. How it is possible?

I tried like this but showing error.

---

Code Verilog - [expand]
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module top
{
input clk,
input rst
};
wire a[0:10];
sub dut( . clk(clk),
           .rst(rst),
           .a(a)
          ); 
endmodule

---

 

[dave_59]

Show us the sub dut, and show us your error.

 

[ads-ee]

You dont even tell us what the error is, how do you expect anyone to help? Just a guess but your a SW type that's used to C syntax and used to using {} instead of (). If that was just a typo then you should have included the sub module and the reported error from whatever tool you used.

Regards

 

[gnoble29]

My sub module will be as follows

---

Code Verilog - [expand]
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Module sub(input clk, input rst, output reg a[0:10]);
reg i;
always @(posedge clk)
begin
 
for (i=0;i<10;i=i+1)
begin
a[i]=1’b0;
end
 
end
endmodule

---

My aim is to initialize an array to zero by using submodule. But I am not able to pass the array since it showing the error “Illegal reference to memory: a”.

 

[ads-ee]

because you have this in the code.

.a(a)

you can't pass an array through verilog module ports. In my opinion this is the biggest flaw of Verilog and should have been changed in 2001. Systemverilog supports arrays passed through module ports, but I'm not sure how well supported it is. Modelsim supports it but I'm pretty sure ISE doesn't and Vivado doesn't (I'll admit I haven't tested it on Vivado) not sure about Quartus II. If you stick with Verilog you'll have to perform conversions of the array to a bus then back again.

Sorrry, I didn't notice the array the first time I looked at your code, though I did notice the {} ;-).

 

[gnoble29]

Thanks ads_ee for your quick reply.
Can you explain little bit about array to bus conversion and its implementation in verilog?

 

[nikhilna007]

it will not work in Quartus II

 

[ads-ee]

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Code Verilog - [expand]
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// a_bus is used to transfer data through the module ports
wire [15:0] a_bus;
wire a_array[0:15];
 
integer i;
for (i=0;i<16;i=i+1) begin
  // convert array values to bus
  a_bus[i] = a_array[i];
  // convert bus back to array
  a_array[i] = a_bus[i]
end

---

If you have a 2d array:

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Code Verilog - [expand]
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wire [16*8-1:0] a_bus;
wire [7:0] a_array[0:15];
 
integer i;
for (i=0;i<16;i=i+1) begin
  // convert array of bytes to bus
  a_bus[8*i +:8] = a_array[i]; //a_array[i][7:0]
  // convert bus back to array of bytes
  a_array[i] = a_bus[8*i +:8];
end

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