initialize array verilog
hi Naz,
the 1st thing which you should correct is you have declared the array as reg which should be wire since you are initializing the array outside the always block. and another thing don't use parameter...
use `define or simple assign statement.
another thing you have defined stimulus module twice...
Here is the code:
////////////(main.v) file
module main(out1,out2,in);
output [1:0] out1;
output [1:0] out2;
input in;
reg [1:0]out1;
reg [1:0]out2;
wire [1:0] a[0:1];
`include "define.v"
always @(in)
begin
if(in==0)
out1=a[0];
if(in==1)
out2=a[1];
end
endmodule
///////////////////////////////
module stimulus();
wire [1:0] out1;
wire [1:0] out2;
reg in;
main mm1(out1,out2,in);
initial
begin
# 10 in=0;
#10 in=1;
#10;
end
endmodule
2nd file
//////////////////define.v file///////////////
//assign a[0]=2'b01;
//assign a[1]=2'b10;
OR
`define a[0] 2'01;
`define a[1] 2'10;
/////////////////////////////////////////////////
you can use either assign statement or `define. both will work
Haneet