Array For Large Values

[RAVI30]

hi..
if we uses a large value of array ... then it will uses RAM/ROM memory or flip-flops ..
what is the max size of array we can use in our design... device spartan-3A...

 

[TrickyDicky]

How much ram does the device have? thats the largest array you have, IF the code is written correctly.

 

[RAVI30]

in LDPC implementation we need to calculate the 8 address location of Parity bit array and fetch the value for that location and xor with input data and again assign the result to that locations only....... ...
i have tried to assign but it was not assign .... only one value is assigning and other all is assigning XXXX......if it will assigning one signal at one cycle then delay will so much..........i have tried both this methods.........
and one more if i need RAM then also there will we can assign the only 2 address at one cycle by using dual port RAM......
plz help me in assign the multiple signal in one clock cycle....

 

[TrickyDicky]

Your post still doesnt make much sense. In a ram you can only assign one value in the array in a single clock cycle. You could of course use multiple rams in parrallel.

Post some code with some better questions and maybe we can help.

 

[FvM]

You can safely assume that others have implemented LDPC encoders in FPGA before. As I mentioned in one of your previous threads, you probably need to restructure the problem.

 

[RAVI30]

like this i need to compute around 7 to 8 time and assign the signal to the parity bit array all will done in one cycle



process(clk,reset)
begin
if(clk'event and clk= '1') then
if(reset='1') then
i<=0;
s<=0;
p12<='0';

else
s<=y_6;
i <=((t*Qldpc)+(LDPC_ParityBitAddress(s))) mod (Nldpc-Kldpc);
p(i)<= p12 xor DataIn;
end if;
end if;
end if;
end process;

 

[TrickyDicky]

if, for some strange reason, you MUST complete the i calculation in a single clock cycle, use a variable for i. But your FMAX is going to be very very slow (say 10-20MHZ). Mostly because of the mod operation.

IF you want to increase the fmax, you need to pipeline this design (as I am sure other enginseers have done).

 

[RAVI30]

kk...
i removed MOD operation and used alternate method ... but now new issue is to assign multiple signals/values to calculated address locations......

i need to assign around 8 different values in different locations .... but i have able to assign only one value to one location ....
please give so information about assigning multiple signals....

 

[TrickyDicky]

you need to post some code so we can understand exactly what you're doing. You question is not very clear. Are these locations in the same memory or can you parralellise them into separate memories?

Have you drawn the circuit diagram out before you started writing code?

 

[RAVI30]

if i used different memory then at last i need to send the values to output by XOR ing previews and present location data like

if(count > 162000 )then
p4 <=p(e) xor p(e-1);
e<= e+1;
end if;

and the some time the values will be replaced by new values......



process(clk,reset)
begin
if(clk'event and clk= '1') then
if(reset='1') then
i<=0;
s<=0;
p12<='0';

else
s<=y_6;
i <=((t*Qldpc)+(LDPC_ParityBitAddress(s))) mod (Nldpc-Kldpc);
p(i)<= p12 xor DataIn;
end if;
end if;
end if;
end process;


like this around 8 calculation in one cycle....

 

[TrickyDicky]

You're trying to write code as if it were software. You need to take a step back, and think about the hardware - what memories, registers, adders are you going to need. Draw the circuit out on paper and only then write any VHDL.

 

[RAVI30]

k... then delay will more.....