farzanehjun
Junior Member level 1
Hi every one
I designe waveguide slotted array with -27.5 dB SLL in CST,
when I fabricate and test it
SLL increase to -25 dB
Have any one information about space tapering or other methods to reduce SLL in simulation?
I designe waveguide slotted array with -27.5 dB SLL in CST,
when I fabricate and test it
SLL increase to -25 dB
Have any one information about space tapering or other methods to reduce SLL in simulation?