argh,,,quartus2 7.1 gimme headache...assist plis

[bend wh0nx]

here's my code for my traffic light project...but it doesnt seem to be ok...urgh





library IEEE;
use IEEE.std_logic_1164.all;

entity Vsvale is
port ( CLOCK, RESET, NSCAR, EWCAR, TMSHORT, TMLONG: in STD_LOGIC;
OVERRIDE, FLASHBACK: in STD_LOGIC;
NSRED, NSYELLOW, NSGREEN: out STD_LOGIC;
EWRED, EWYELLOW, EWGREEN, TMRESET: out STD_LOGIC );
end;

architecture Vsvale_arch of Vsvale is
type Sreg_type is (NSGO, NSWAIT, NSWAIT2, NSDELAY,
EWGO, EWWAIT, EWWAIT2, EWDELAY);
signal Sreg: Sreg_type;
begin

process (CLOCK)
begin
if CLOCK'event and CLOCK = '1' then
if RESET = '1' then Sreg <= NSDELAY; else
case Sreg is
when NSGO =>
if TMSHORT='0' then Sreg <= NSGO;
elsif TMLONG='0' then Sreg <= NSWAIT;
elsif EWCAR='1' and NSCAR='0' then Sreg <= NSGO;
elsif EWCAR='1' and NSCAR='1' then Sreg <= NSWAIT;
elsif EWCAR='0' and NSCAR='1' then Sreg <= NSWAIT;
else Sreg <= NSGO;
end if;
when NSWAIT => Sreg <= NSWAIT2;
when NSWAIT2 => Sreg <= NSDELAY;
when NSDELAY => Sreg <= EWGO;
when EWGO =>
if TMSHORT='0' then Sreg <= EWGO;
elsif TMLONG='1' then Sreg <= EWWAIT;
elsif NSCAR='1' and EWCAR='0' then Sreg <= EWGO;
elsif NSCAR='1' and EWCAR='1' then Sreg <= EWWAIT;
elsif NSCAR='0' and EWCAR='1' then Sreg <= EWWAIT;
else Sreg <= EWGO;
end if;
when EWWAIT => Sreg <= EWWAIT2;
when EWWAIT2 => Sreg <= EWDELAY;
when EWDELAY => Sreg <= NSGO;
when others => Sreg <= NSDELAY;
end case;
end if;
end if;
end process;
end Vsvale_arch;

i keep on receive this error...
i've defined the top entity at the first place,,,

helpppppp...
thanx
bend wh0nx