1) in digital we can use any orientation , but in analog we should follow same orientation.
2) DRC and LVS no problem , but overlapping will produce parasitic capacintance that increases delay, as possiblly we must avoid overlapping.
i think these are correct . can anybody comment pls.
Added after 1 hours 40 minutes:
we can follow different orientations in digital, but in anlog only we must follow same orientation for matched transistors, because the transconductances of the transistors are same which are placed in same orientation, this will avoid current mismatches.