Are processes REALLY sequential in VHDL ?

[Dijskstra]

I have 2 questions about VHDL processes:


Question 1 - Are processes REALLY sequential ?

Let's suppose that I have the little code below:

process (sensitivity list)
begin
    bit0 <= 1;
    delay(1000); -- delay is a user function to pause the program (in this case 1000 ms)   
    bit1 <= 1;
end process;

Can I have 100% certain that bit1 is assigned with '1' after bit0 or inside the process the statements are concurrent ?



Question 2 - What happen if the signals of the sensitivity list change in the middle of a process ?

process (clk)
begin
    if (clk'event and clk='1') then
        ...
        statement1;
        statement2;
        statement3;
        ...
        statement500      -- here clk rises again
        ...
        statement998;
        statement999;
        statement1000;
    end if;
end process;

Lets suppose that the execution time of the process is bigger than the clock period.

If CLK rises in the middle of the process, the code "jump" to the start of the process, or continue until the end, ignoring the rising edge of CLK ?


Thank you.

Anders

 

[std_match]

Statements in a process executes in zero time. In simulation only you can do tricks like "wait", and the process will ignore the sensitivity list until it finishes.

This means that for synthesizeable code the whole process executes in zero time.

 

[TrickyDicky]

To answer this question, you also need to understand the difference between a signal and variable, and also the concept of delta cycles.

1. Signal and variable differences:
A variable is updated immediately, while a signal is only scheduled to be updated at a future point in time, at a minimum of 1 delta cycle later. If multiple assignments are made to a signal in the same delta cycle, then it is the last one that is assigned.

2. Delta cycles.

An HDL simulation (so this applies to verilog too) runs using a concept of delta cycles - ie. an infinitely small partition of time. A process executes statements sequentially in an infinite loop, and if there are no wait statements or senitivity list, the process will loop forever within the same delta. (a compiler warning will be thrown for this in simulation only). Hence why there is no "execution time" in the second process you describe. Because you have clk in the sensitivity list, it is illegal to have wait statements within the process.

So, if a process has a sensitivity list, it will only "execute" once, when the signal in that list has a 'event, and all statements occur inside the same delta cycle. All of the statements are evaluated, and then it waits until there is another 'event on clock.

- - - Updated - - -

Statements in a process executes in zero time. In simulation only you can do tricks like "wait", and the process will ignore the sensitivity list until it finishes.

No it wont, because it's illegal to have a sensitivity list and wait statements in the same process, you can have one or the other.