Are normal buffers sized for equal rise and fall times

[identical]

If they are sized for equal fall and rise times then why are clock buffers made seperately (Sized for equal rise and fall times). If they aren't sized for equal fall and rise times then why do we need asymmetrical fall and rise times for a normal inverter or buffer.

 

[ThisIsNotSam]

If they are sized for equal fall and rise times then why are clock buffers made seperately (Sized for equal rise and fall times). If they aren't sized for equal fall and rise times then why do we need asymmetrical fall and rise times for a normal inverter or buffer.

I have seen libraries with all variations you can think of, both for clock and for regular signals.

 

[identical]

I have seen libraries with all variations you can think of, both for clock and for regular signals.

On average, what is the key difference between the two apart from drive strength.

 

[oratie]

Regular buffers are trade-off between minimal delay, equal rise/fall delay/transition, minimal power, cell area.
Clock buffers optimized more for equal rise/fall delay/transition (others are less priority).