Jan 30, 2007 #1 K kunal1514 Full Member level 1 Joined Dec 13, 2006 Messages 98 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 2,027 Functions Can any body tell me whether "Functions" in verilog are synthesizable or not if yes provide me some relevant proof. it's urgent.
Functions Can any body tell me whether "Functions" in verilog are synthesizable or not if yes provide me some relevant proof. it's urgent.
Jan 30, 2007 #2 A atmaca Full Member level 4 Joined Jan 13, 2004 Messages 211 Helped 4 Reputation 8 Reaction score 2 Trophy points 1,298 Activity points 1,556 Re: Functions it depends on the compiler u use
Jan 30, 2007 #3 B beta0 Member level 5 Joined Nov 24, 2003 Messages 88 Helped 7 Reputation 14 Reaction score 2 Trophy points 1,288 Activity points 393 Functions Sometimes we use the "Function" to emplmention combinational circuit.
Jan 31, 2007 #4 A aji_vlsi Advanced Member level 2 Joined Sep 10, 2004 Messages 643 Helped 85 Reputation 170 Reaction score 12 Trophy points 1,298 Location Bangalore, India Activity points 4,944 Re: Functions kunal1514 said: Can any body tell me whether "Functions" in verilog are synthesizable or not if yes provide me some relevant proof. it's urgent. Click to expand... Functions when used in RTL context (meaning no use of $time etc) are fully synthesisable. WHat "proof" do you need? For whom? Refer to IEEE 1364.1 standard if needed. Or use your synthesis tool as a proof. HTH Ajeetha, CVC www.noveldv.com
Re: Functions kunal1514 said: Can any body tell me whether "Functions" in verilog are synthesizable or not if yes provide me some relevant proof. it's urgent. Click to expand... Functions when used in RTL context (meaning no use of $time etc) are fully synthesisable. WHat "proof" do you need? For whom? Refer to IEEE 1364.1 standard if needed. Or use your synthesis tool as a proof. HTH Ajeetha, CVC www.noveldv.com