# Arbitrary binary counter that counts to 800 and resets to zero

Status
Not open for further replies.

#### raidfibre

##### Newbie level 1
I am attempting to make an arbitrary counter that can, for example, count to 800 and reset to zero. Do I want a counter with an asynchronous reset or __ ? I'm a little confused. I have one that works but when I synthesize it I get a message that I have a gated clock. I will post my code for that tomorrow (it's on my laptop). But if anyone has a quick couple of words for me I would appreciate it.
Thanks a lot
--
MK

#### neoaspilet11

##### Full Member level 5
binary counter

Hi,
I think you mean a presettable binary counter. If your max count is 800 your counter must be at least 10 - bit wide to give you a maximum possible count of 2^10 - 1. If you want to reset the count at 800. make a combination logic at the counter ouputs such that it will give a reset signal when the count is 800. All you need to do is build a single bit binary counter and cascade it 10 times.

Hope this help

#### Black Jack

##### Full Member level 4
Re: binary counter

raidfibre said:
I am attempting to make an arbitrary counter that can, for example, count to 800 and reset to zero. Do I want a counter with an asynchronous reset or __ ? I'm a little confused. I have one that works but when I synthesize it I get a message that I have a gated clock. I will post my code for that tomorrow (it's on my laptop). But if anyone has a quick couple of words for me I would appreciate it.
Thanks a lot
--
MK
I think that projects must be synchronous as possible. So you need synchronous counter and comparator with DFF at output. Inputs A of Comparator connect with outputs of Counter. Inputs B of Comparator is (Constant-1). Output of DFF connect with Synchronous Reset of Counter.

#### echo47

binary counter

When using FPGA, try to do everything synchronously.

You didn't say what should happen after the counter resets to zero.
Here's a Verilog counter that endlessly counts 0 to 800, 0 to 800, etc.
Code:
module top (clk, count);
input             clk;
output reg  [9:0] count=0;

always @ (posedge clk) begin
count <= (count == 800) ? 0 : count + 1;
end
endmodule

Status
Not open for further replies.