For simulation, you'll have to add a couple of pullups to the sda and scl lines. If you don't then the high signal levels will show as Z's in the simulation.
entity i2c_master_top isgeneric(
ARST_LVL :std_logic:= '0'
);port(// other stuff
scl_pad_i :instd_logic;-- i2c clock line input
scl_pad_o :outstd_logic;-- i2c clock line output
scl_padoen_o :outstd_logic;-- i2c clock line output enable, active low
sda_pad_i :instd_logic;-- i2c data line input
sda_pad_o :outstd_logic;-- i2c data line output
sda_padoen_o :outstd_logic-- i2c data line output enable, active low);endentity i2c_master_top;
since it is inout.i m confused ,what should i connect to its input?
Just wanted to warn people to be careful with using I2C fpga core as the voltage of I2c can be 5V pullup and most FPGA's these days don't go that high.
sda_pad_i would be used to read data back from the DAC, if it allows reading.
I also have used the master I2C core (pre-wishbone interface) in a design. We had absolutely no problems controlling an RF module that was attached to our board. In our case the FPGA was the bridge between the 16-bit uProcessor and the I2C. As it was a bridge I didn't need to create an FSM to control any flash device.