Anyone knows the .meas for measuring the PLL jitter

[asicpark]

Hi all,

I was told that the PLL jitter can be measured from the trasient simulation result using the .meas statement. But I don't know how to make it. Does anyone give me the example for it?

Thanks in advance.

 

[yankuangtu]

trasient simulation itself don't include any noise source,so you cann't just use it to simulate jitter

 

[derekqiao]

I've same question, too.
Could you add noise source in tran simulation?

 

[yaxazaa]

measuer the period of the vco output, and do statistical analysis.

 

[bbqsky]

Hi, I tell you the method.

You can use the "Eye diagram" function of the calculator. The period of the Eye diagram is your pll locked period.

 

[asic_ant]

hope this will help : D
Best regards!

 

[lovseed]

I've same question, too.
Could you add noise source in tran simulation?

What we does is to add series inductors on power/ ground nodes to simulate the package inductor and the inductors in the power rail, usually we include 10nH inductor. Also you can include inductors to all the input and output pins.

To measure the Jitter, you can use .measure,but troublesome. If your measure failed you need to rerun the un-endurable long simualtion. I recommend another good method.

You can just simulate the PLL without any .measure statement and view the waveform in cscope, then use the "At Y" measurement function in cscope, you can save the "At Y" measurement result. It is a series of time point at the Y value you specified.
Then you can write perl script to handle these measured data to obtain long-term jitter, short term jitter, cycle-to-cycle jitter, etc.

It is really a good process which I have tried and found out in real design experience.And the result is very close to silicon result.

Good Luck!