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Anyone know how to improve IIP3? CMOS LNA desig

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dd2001

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IIP3 issue?

Design a CMOS LNA, got IIP3=1.5dBm, Which don't meet the requirement? Anyone know how to improve IIP3?
 

Re: IIP3 issue?

You have to be more specific. What frequency? What transistors are used? At what bias (drain voltage and drain current if a FET or GaAs FET is used).

In some cases increasing the drain current for a FET may improve IIP3, but then noise figure can be degraded.
 

Make it differential, increase Vsg-Vt, moderate your gain ... as simple as it is :)

nathan
 

the most common method is to use feedback, for example using inductor, resistor or capacitor as emitter(or source) degeneration. of course increasing current is a method. however, it all depends on your circuits and your requriements, especially other specs. There are tradeoffs betwenen linearity, noise and gain.
 

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