Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Anyone familiar with the jitter simulation?

Status
Not open for further replies.

beabroad

Member level 4
Joined
Nov 24, 2003
Messages
76
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,288
Activity points
628
Including how to generate jitter at the source, and test the jitter tolerance, transfer, generation at the receiver end, preferably implemented in Matlab.

The application would be PON network, especially the OLT clock recovery circuit.

Thanks for your help, any paper or application notes would be good.
 

Just add a white noise in signal phase, for example, the idle signal edge at time [1 4 8 12] that signal is [0 0 0 1 1 1 1 0 0 0 0 1 1 1 1], you can add a white noise at the edge that the result signal is [0 0 0 0 1 1 1 0 0 0 1 1 1 1 1], and you can derive the relation between white noise variance with the jitter variance
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top