Anybody with FIB experience please help!

[sharkies]

I need to cut and reconnect a wire in my digital logic.
the distance is short, just about couple um.
However, it has to reach all the way down to metal 1.
Does anybody know what the yield rate is for doing fib on the lowest metal layer?
Can anybody recommend a good company for this task?

 

[erikl]

... Does anybody know what the yield rate is for doing fib on the lowest metal layer?
Can anybody recommend a good company for this task?

Yield rate: depends on a lot of parameters which you didn't care to mention: process size, # of metal layers, size of end points, ...

An example: we got 8 good ones out of 10, with 3 interruptions and new connections (on each chip) on min. size end points in M2 & M3 of a 5M 0.18µm design (4 years ago, German semicond. institute).

May be this is of interest to you?

 

[sharkies]

it's 65nm with 9metal layer. the wire should be .1um wire width. I'm thinking of getting it fibbed from the back of the chip

 

[quantized]

I need to cut and reconnect a wire in my digital logic.
the distance is short, just about couple um.
However, it has to reach all the way down to metal 1.
Does anybody know what the yield rate is for doing fib on the lowest metal layer?
Can anybody recommend a good company for this task?

Ask around for "flip chip FIB". There are companies that can FIB in from the back (substrate) side which would get you to metal-1 without disturbing the metal above it (which probably carry power, clock, etc).

Of course this will utterly destroy any transistors underneath the metal-1 you're trying to access.

Last time I asked about this I seem to remember the figure 5um being kicked around for the region of substrate destruction.

 

[sharkies]

what does this mean?
"Last time I asked about this I seem to remember the figure 5um being kicked around for the region of substrate destruction."

Also, can you make connections from the backside of the chip?

 

[diarmuid]

Can anybody recommend a good company for this task?

In my FA days I used use this crowd a lot. Never had any problems with them:

https://portal.tugraz.at/portal/page/portal/felmi/research/FIB

 

[erikl]

Here's another one in Germany, which we formerly used with good success:

**broken link removed**

 

[zywts]

do not know. but, if you deals with the vendor. get the technical support from that vendor. tell them a bit about your process. they have a good idea about the yield. if it is too difficult, some time they will try and some time they will just say no.

 

[quantized]

what does this mean?
"Last time I asked about this I seem to remember the figure 5um being kicked around for the region of substrate destruction."

When they FIB through the back of the chip, they're basically blasting a 5um wide hole in the silicon. So any transistors in that area are destroyed.

Also, can you make connections from the backside of the chip?

Yes, that's the idea.