Thanks, so do you basically enthuse that we can say goodbye to primary RCD clamps in offline Flyback converters up to 150W and beyond?
I mean, we can just let the FET avalanche and dissipate the energy.
I thought an avalanched FET is in danger of latching ON its internal PNP transistor?
We have a flyback prototype sent to us with Ipk(pri) = 4.4A, fsw = 30khz, and L(leak) =9.1uH.
Thats a leakage energy of 0.088mJ every 33.3us
Or a leakage power of 2.64W
It still seems impossible to know if the IPD95R450 NFET can handle this from the info given in its datasheet....
IPD95R450 NFET
.though from the graph on page 9 it looks like it possibly can up to 126 degc Tj. Though that graph doesnt say whether or not it refers to repetitive or single avalanche event?
Also, all the datasheets avalanche readings seem to be at 50V drain voltage, which seems strange when its a 950V FET.....presumbaly avalanche enrgy reduces as Drain to source voltage increases?
Others here have kindly commented here that its difficult to assess how much of the leakage energy goes into the avalanche as some of it goes into the fet capacitances.