Apr 9, 2009 #1 N nagu guptha Junior Member level 2 Joined Dec 5, 2008 Messages 21 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,410 verilog... Do we have any provision of signal attributes in verilog, like 'event in vhdl. Is it possible to check positive edge of clock in behavioural statements like TASK and conditional IF statements. please do reply.....
verilog... Do we have any provision of signal attributes in verilog, like 'event in vhdl. Is it possible to check positive edge of clock in behavioural statements like TASK and conditional IF statements. please do reply.....
Apr 9, 2009 #2 J jbeniston Advanced Member level 1 Joined May 5, 2005 Messages 460 Helped 106 Reputation 214 Reaction score 73 Trophy points 1,308 Activity points 3,494 verilog... 'event is similar to @ in Verilog. @(posedge signal); Will wait for a postive edge on signal. This can be used in tasks.
verilog... 'event is similar to @ in Verilog. @(posedge signal); Will wait for a postive edge on signal. This can be used in tasks.
Apr 10, 2009 #3 N nagu guptha Junior Member level 2 Joined Dec 5, 2008 Messages 21 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,410 Re: verilog... Thank you for replying......,it was a useful information.
Apr 10, 2009 #4 F flanix Newbie level 5 Joined Jun 18, 2007 Messages 9 Helped 2 Reputation 4 Reaction score 0 Trophy points 1,281 Activity points 1,311 verilog... that is right!