Feb 17, 2015 #1 K kah89 Junior Member level 2 Joined Feb 9, 2015 Messages 24 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 169 Hi Does any materials regarding non overlapping clocks design?
Feb 17, 2015 #2 leon30 Junior Member level 1 Joined Mar 26, 2010 Messages 16 Helped 4 Reputation 8 Reaction score 4 Trophy points 1,283 Activity points 1,437 Hello, Please see this link https://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-tpcg/two-phase-clock-gen_print.html Two non-overlapping clock signals usually are made from 1 clock signal that goes through SR NOR or SR NAND latch with delay buffers in the loops, and bare in mind that S and R signals should be inverted.
Hello, Please see this link https://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-tpcg/two-phase-clock-gen_print.html Two non-overlapping clock signals usually are made from 1 clock signal that goes through SR NOR or SR NAND latch with delay buffers in the loops, and bare in mind that S and R signals should be inverted.
Feb 22, 2015 #3 K kah89 Junior Member level 2 Joined Feb 9, 2015 Messages 24 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 169 leon30 said: Hello, Please see this link https://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-tpcg/two-phase-clock-gen_print.html Two non-overlapping clock signals usually are made from 1 clock signal that goes through SR NOR or SR NAND latch with delay buffers in the loops, and bare in mind that S and R signals should be inverted. Click to expand... Thank you. It was helpful.
leon30 said: Hello, Please see this link https://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-tpcg/two-phase-clock-gen_print.html Two non-overlapping clock signals usually are made from 1 clock signal that goes through SR NOR or SR NAND latch with delay buffers in the loops, and bare in mind that S and R signals should be inverted. Click to expand... Thank you. It was helpful.